Ampere Computing M128-30 Altra Max TSMC 7 nm FinFET Server Processor Digital Floorplan Report

Product Code
Release Date
Product Item Code
Device Manufacturer
Ampere Computing
Device Type
Applications Processor
Report Code
This report presents a digital floorplan analysis (DFR) of the Ampere Computing M128-30 Altra Max TSMC 7 nm finFET server processor, and includes an analysis of the floorplan layout and standard cell libraries used in the major IP blocks, including SRAM memory usage overview.
This report contains the following detailed information:
  • Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
  • Scanning electron microscopy (SEM) plan-view micrographs showing the layout of the die at different levels, including fin/shallow trench isolation (STI), gate, contacts, and minimum pitch metals
  • Measurements of horizontal dimensions of some of the major layout features, particularly the pitch and track height of standard cells
  • Plan-view optical micrograph of the die delayered to the metal gate level
  • Identification of major functional blocks on a gate level die photograph
  • Table of functional block sizes and percentage die utilization
  • High-resolution top metal and gate level die photographs delivered in the CircuitVision software
  • Cost of die based on the manufacturing cost analysis of the observed process
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