Gyrfalcon Technology Lightspeeur 2803S AI Accelerator TSMC 28 nm HPC+ HKMG CMOS Process Digital Floorplan Analysis

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Gyrfalcon Technology
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This report presents a digital floorplan analysis (DFR) of the Gyrfalcon Technology Lightspeeur 2803S AI Accelerator. This second-generation chip boosts performance to nearly 17 TOPS from the first generation 2801. Additionally, the company has now added IP licensing to its portfolio as synthesizable RTL or as 28 nm hard macros.
This report contains the following detailed information:
  • Selected teardown photographs, package photographs, package X-rays, die markings, and die photographs
  • Scanning electron microscopy (SEM) plan-view micrographs showing the layout of the die at different levels, including fin/shallow trench isolation (STI), gate, contacts, and minimum pitch metals
  • Measurements of horizontal dimensions of some of the major layout features, particularly the pitch and track height of standard cells
  • Plan-view optical micrograph of the die delayered to the metal gate level
  • Identification of major functional blocks on a gate level die photograph
  • Table of functional block sizes and percentage die utilization
  • High-resolution top metal and gate level die photographs delivered in the CircuitVision software
  • Cost of die based on the manufacturing cost analysis of the observed process
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